Power management is an important aspect of processor design, especially as the designs of such processors become ever more complex and the demand for small, battery-powered consumer devices such as mobile phones increases. One way to control power consumption is to change the processor's clock speed, some general examples of which can be found in JP 2006-11697 (Nakamura), US 2003/0131268 (Kolinummi et al), US 2004/0025067 (Gary et al), and US 2002/0087897 (Cline et al).
For example, Kolinummi describes a programmable power control register containing information about powered down-modes for different hardware units, one of the hardware units being a CPU. The powered down mode may affect the clock frequency supplied to the hardware unit.
If a processor runs too fast, there may be wasted clock cycles and therefore wasted power (especially as running at high frequency requires a higher voltage than operating at lower frequencies). But on the other hand, sometimes a processor will need to run at full speed. It would be advantageous to provide a more flexible system for controlling a processor's clock speed.